The present invention relates to a semiconductor device, and is preferably applicable to, for example, a semiconductor device having a capacitive element.
In some semiconductor devices, a microcomputer is formed in one semiconductor chip. In the semiconductor chip including a microcomputer formed therein, there are formed a Central Processing Unit: CPU including logic circuits such as a CMISFET (Complementary Metal Insulator Semiconductor Field Effect Transistor), memories, analog circuits, or the like.
As the memory used in the semiconductor chip, for example, an electrically rewritable nonvolatile memory is used. As the electrically erasable/writable nonvolatile memory (nonvolatile semiconductor storage device), an EEPROM (Electrically Erasable and Programmable Read Only Memory) or a flash memory has been widely used.
In order to operate the nonvolatile memory as described above, a driving circuit such as a booster circuit is formed in a semiconductor chip. The driving circuit requires a high-precision capacitive element. Further, in the semiconductor chip including a microcomputer formed therein, an analog circuit is also formed. The analog circuit also requires a high-precision capacitive element. Therefore, in the semiconductor chip, capacitive elements are also formed other than the nonvolatile memory and the MISFET.
Some such capacitive elements are formed simultaneously with the nonvolatile memory cell using a step of manufacturing the nonvolatile memory cell. Specifically, in the step of forming the control gate electrode of a nonvolatile memory cell, the lower electrode of the capacitive element is formed. In the step of forming a lamination film including a charge accumulation film of the nonvolatile memory, the capacitive insulation film of the capacitive element is formed. Then, in the step of forming the memory gate electrode of the nonvolatile memory cell, the upper electrode of the capacitive element is formed. The capacitive element is called a PIP (Polysilicon Insulator Polysilicon) capacitive element because a polysilicon film is used for the upper electrode and the lower electrode.
In Japanese. Unexamined Patent Publication No. 2009-99640 (Patent Document 1) and Japanese Unexamined Patent Publication No. 2011-40621 (Patent Document 2), there is disclosed a PIP capacitive element having a lower electrode and an upper electrode each formed of a polysilicon film formed over a semiconductor substrate, and a capacitive insulation film formed of, for example, a silicon oxide film, formed between the lower electrode and the upper electrode.
The Patent Document 1 discloses the following: in the upper electrode, there are an overlapping region whose underlying layer includes the lower electrode present therein, and a non-overlapping region whose underlying layer includes no lower electrode present therein; and the plug to be coupled with the upper electrode is formed in the non-overlapping region of the upper electrode. Whereas, the Patent Document 2 discloses the following: the lower electrode, the capacitive film and the upper electrode are stacked in this order; and a via is coupled with the upper electrode over the lower electrode.